1. Field of the Invention
The present invention relates to an anti-fuse device and memories, and more particularly, to aggregate area oxide breakdown by enhancing electrical fields near the drain junction, by making channel region more uniform, or by applying alternative polarities of voltage pulses so that program area can be more restricted and programming can be more reliable.
2. Description of the Related Art
One-Time Programmable (OTP) devices can be programmed into a different logic state once and only once in the lifetime. OTP devices allow every integrated circuit die being customized after fabrication. They can be used for chip ID, security key, device trimming, feature selection, memory redundancy, or Programmable ROM (PROM) for Micro-Controller Units (MCUs). Laser fuse is one of the old and mature OTP technologies that has been used widely since 1980s. However, the laser fuse has a large cell size of 150 um2 and can not be shrunken.
As CMOS technologies are scaled, the gate oxide becomes thinner and thinner. In the 65 nm CMOS technology, the gate oxide is only about 15 Å, or 1.5 nm, thick. For such a thin gate oxide, the gate oxide can be easily broken down and be conductive to the silicon substrate by a high voltage during handling or under ESD zapping. However, this property can be turned into constructive applications by using gate oxide breakdown as a One-Time-Programmable (OTP) anti-fuse.
FIG. 1 shows a cross section of a 1.5 T gate oxide breakdown anti-fuse cell 20 according to a prior art. The anti-fuse 20 has an MOS access device 30 and a MOS program device 40 fabricated in standard CMOS processes. The MOS 30 has a polysilicon gate 31 coupled to an Access Wordline (WLA), an N+ source 32 coupled to a bitline (BL), and an N+ drain 33. The MOS 40 has a polysilicon gate 41 coupled to a Program Wordline (WLP), a source 42 coupled to the drain 33 of MOS 30, and a floating drain 22 coupled to a shallow trench isolation (STI). Since the MOS 40 does not have a drain junction, this device is considered half a transistor such that the anti-fuse cell 20 has only 1.5 Transistors (1.5 T). If high voltages are applied to WLP and WLA, and a low voltage is applied to BL, the low voltage can be passed to the source 42 of MOS 40 such that a high voltage will be created between the source 42 and the gate 41 of the MOS 40 to cause oxide breakdown. Before programming there is no conduction path between BL and WLP, when WLA is turned on. However, after programming there can be a conduction path between BL and WLP created, when WLA is turned on. These two conditions represent states 0 and 1, respectively.
Both MOS devices 30 and 40 in FIG. 1 can be fabricated as Lightly Doped Drain (LDD) devices. LDD is a technique to reduce high electrical field near the source or drain junction to alleviate short channel effects so that MOS devices can be scaled further. To fabricate an LDD device, a light dose N− is implanted into MOS regions 26 after polysilicon gates 31 and 41 are patterned and etched. Then spacers 24 are built along the edges of polysilicon gates 31 and 41 near the source and drain regions, i.e. 32 and 33 of MOS 30, and 42 of MOS 40, by depositing oxide or nitride and then etching anisotropically. With spacers 24, the heavy N+ source/drain implant can not penetrate into the lightly-doped regions 26 underneath the spacers so that the lightly doped regions between the source/drain and channel of a MOS act as a buffer to subdue the electrical field near the source/drain junctions. This allows a MOS device being scaled further. To prevent punch-through, a halo implant 27 is implanted underneath the LDD region 26 to create a heavy P+ region to reduce leakage between source and drain, such as 32 and 33 of MOS 30. Generally, the halo implant 27 shares the same mask as the LDD implant 26 in today's CMOS technologies such that P+ halo implant 27 always comes with N− LDD implant 26 into the same area.
A prior art OTP as shown in FIG. 1 suffers many drawbacks. There are three possible program areas 21 in the MOS program device 40, namely LDD 26, halo 27, and channel 28 regions. When a low voltage is passed to the source 42 of the MOS 40 and a high voltage is passed to the gate 41 of the MOS 40, a high electrical field may possibly breakdown the gate oxide in the LDD 26, halo 27, or channel 28 regions. As a result, the program behavior becomes very unpredictable and the conductive current between BL and WLP varies substantially when WLA is turned on. The programming yield is not very high.
Another problem is the so-called oxide “soft breakdown” as shown in FIG. 2(a), referred to Ben Kaczer, et. al, “Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability,” in IEEE Trans. on Elec. Dev., 49(3) 500-507, March 2002. Ideally, a gate oxide should be broken down in the dielectrics to create a permanent short by a high voltage applied, the so-called “hard breakdown” as shown in FIG. 2(b). However, in the most cases, the gate oxide seems conductive after applying a high voltage across a thin oxide film. But the gate oxide may become non-conductive again after cycling or burned in. The physical mechanism of a soft breakdown is very complicated. FIG. 2(a) shows a very simple and intuitive explanation. When a high voltage is applied across a thin oxide, the positive high voltage attracts electrons from the silicon substrate into the oxide. The electrons are piled up in the oxide and form a conductive path such that the oxide appears to be shorted. But those electrons are just temporarily trapped and lined up in the oxide to form a conductive path. Furthermore, this conduction path prevents oxide hard breakdown in other areas. Those charges can be easily returned to substrate after cycling many times so that the state 1 may become state 0 again. The soft breakdown effect makes the gate oxide breakdown anti-fuse very unreliable. This mechanism becomes even worse when the gate oxide is thinner.
FIG. 3 shows another prior art of a split-gate oxide breakdown anti-fuse cell 50. The Access device 30 and the Program device 40 in FIG. 1 are merged into one device 50 in FIG. 3 with a split gate 53—a gate with half thick oxide and half thin oxide near the source 55 and drain 52, respectively. The device 50 has an N+ source 55 coupled to a bitline (BL), a gate 53 with half thick oxide and half thin oxide, and a floating drain 52 near an STI. The source 55 edge has a spacer 54, an LDD region 56, a halo implant region 57 underneath the LDD 56, and a channel region 58. Since the programming happens near the thin oxide region, three possible program areas in FIG. 1 are reduced to only one programming area 51 near the drain 52 to improve program reliability. Though the program yield for the device 50 in FIG. 3 could be better than the device 40 in FIG. 1, the device 50 still suffers the soft breakdown issue. Besides, splitting a gate with half of thick and thin oxides can easily contaminate the delicate gate oxide and make fabrication more complicated. As a result, the yield is not high either.
Accordingly, there is a need to invent an OTP device available in standard CMOS technologies and yet offer small size, high yield, and high reliability to satisfy the requirements of an integrated circuit for most applications.